1. Field of the Invention
The present invention relates to flash electrically erasable programmable read only memories (EEPROM), and more particularly to methods for multi-level cell programming such memories.
2. Description of Related Art
One popular class of non-volatile semiconductor memory is the flash electrically erasable programmable read-only memory (Flash EEPROM). Flash EEPROM technology is based on a memory transistor which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. In this type of memory cell data is stored by altering the amount of charge on the floating gate, which causes the threshold voltage V.sub.t of the memory cell to vary.
The floating gate can hold a range of charge and therefore an EEPROM memory cell can be programmed to any threshold level within a threshold range. The extent of the threshold range, bordered by the minimum and maximum threshold levels of the device, depends on the device's characteristics, operating conditions and history. Each distinct threshold level within the range may, in principle, be used to designate a definite memory state of the cell.
For two-level or two-state EEPROM memory, the transistor serving as a memory cell is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory states are erasable by removing charge from its floating gate upon application of proper voltages. An array of such EEPROM cells is referred to as a "Flash" EEPROM array when an entire array of cells, or significant group of cells of the array, is erased simultaneously (i.e., in a flash). Once erased, a cell can then be re-programmed.
In the usual two-level EEPROM cell, one breakpoint threshold level is established so as to partition the threshold region into two regions. The source/drain current is compared with the breakpoint threshold level that was used when the cell was programmed. If the current read is higher than that of the threshold, the cell is determined to be in a "zero" state, while if the current is less than that of threshold, the cell is determined to be in the other state. Thus, such a two-level cell stores one bit of digital information.
Thus, for a multi-level/analog EEPROM memory cell, each cell stores two or more bits of data. The information that a given EEPROM array can store is thus increased by multiple of number of the states that each cell can store.
Increasing the number of bits that are stored in a single memory cell has several consequences with respect to programming the memory cell. First, the storage of multiple bits in a memory cell typically requires a narrow range of V.sub.t voltages for each state. Over-programming thus becomes a bigger concern, and care must be taken to precisely place the cell into the desired multi-level state. Second, the narrow ranges of threshold voltages V.sub.7 for each state and need for accurate placement of states result in the values of the programming voltage levels being a critical parameter for accurately programming the memory cell. In other words, the programming verification margin must be tightened to a very small range.
EEPROM devices are typically set up as essentially orthogonal arrays of "bit lines" and "word lines" which can be programmably interconnected to achieve a desired logical result. The interconnections can be programmed by addressing the appropriate bit lines and word lines, and transferring the desired programming data to the interconnections by applying to the selected word lines and bit lines a predetermined programming voltage.
For analog/multi-level Flash EEPROM, the cell V.sub.t is programmed with different levels, usually more than two levels. On the other hand, the prior art program algorithm used in some two-level devices is designed to have two levels only. Therefore, a new program algorithm needs to be developed.
The floating gate in Flash EEPROM devices may be charged through a Fowler-Nordheim tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected from the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism, known as hot electron injection, may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate.
The high voltage used to charge the floating gate place significant design restrictions on flash EEPROM devices, particularly as the cell dimensions and process specifications are reduced in size.
The act of charging the floating gate using F-N tunneling mechanism is a relatively slow process that can restrict the application of flash EEPROM devices in certain speed sensitive application.
In prior art floating gate memory architectures using sub-micron technology, the critical dimension variation in patterns on the physical material is usually controlled within about 10%. For a flash EEPROM cell such variation in critical dimensions may result in a variation in programming speed to the second order. Further, if deviation in bias voltages in the array is considered, the variation in programming speed may vary by the fourth order in prior art devices.
Another problem associated with floating gate memory devices arises because the charging of the floating gate is difficult to control over a large array of cells. Thus, some of the cells program more quickly than others in the same device. In a given program operation, not all the cells subject of the operation will settle with the same amount of charges stored in the floating gate. Thus, so called program verify sequences have been developed to efficiently ensure that the memory is being accurately programmed. The program verify operations are based on comparing the data stored in the floating gate memory array with the intended data. The process of comparing data is relatively time consuming, involving sequencing byte by byte through the programmed cells. If a failure is detected in the verify sequence, then the program operation is retried. Program retries are typically executed word-by-word or byte-by-byte in prior art devices. Thus, bits successfully programmed in a byte with one failed bit are subject to the program cycle repeatedly. This can result in over-programming and failure of the cell. Also, when multiple bits per cell are stored, the program operations must be applied several times to establish the multiple threshold levels involved.
The conventional algorithm for programming a flash EEPROM uses a fixed pulse width and fixed bias voltages, with a program verification loop executed after each programming pulse. If the verifying fails, then another pulse is applied in an iterative fashion. In this stage, programming pulses with too much energy will produce over-programmed cells. An over-programmed cell may result in coding error by moving too much charge out of the floating gate. Thus, a good programming algorithm must be carefully designed to avoid over-programming, especially for multi-level devices where, as mentioned above, multi-level threshold voltages need to be programmed in narrow margin ranges. Another consideration for a good programming algorithm is to make sure that it does not take too long time to program a particular byte in the memory.